The present technology relates to a solid-state imaging device represented as a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and a camera system.
It is a main stream for the output circuit of a CCD (Charge Coupled Device) as a solid-state imaging device (image sensor) to be a one channel (ch) output using an FD amplifier having a floating diffusion layer (FD: Floating Diffusion).
Meanwhile, the CMOS image sensor is equipped with an FD amplifier for every pixel, and a column-parallel output type in which a single row line out of a pixel array is selected and these are read out at the same time in the column direction is mainstream as the output thereof.
It may be difficult to obtain a sufficient driving ability in the FD amplifier disposed in the pixel, accordingly, it may be necessary to lower a data rate because a parallel processing is advantageous.
In this way, the CMOS image sensor has been widely used as an imaging device in an imaging apparatus such as digital cameras, camcorders, surveillance cameras or in-vehicle cameras.
FIG. 1 is a diagram illustrating an example of general configuration of a CMOS image sensor in which pixels are disposed in the form of a two dimensional array.
The CMOS image sensor 10 in FIG. 1 is configured by a pixel array unit 11, a row selection circuit 12, and a readout circuit (column processing circuit: AFE) 13.
With respect to the pixel array unit 11, pixel circuits are disposed in a matrix form of M rows×N columns.
The row selection circuit 12 controls the operation of the pixels disposed in an arbitrary row out of the pixel array unit 11. The row selection circuit 12 controls the pixel through control lines LSEL, LRST, and LTRG.
The readout circuit 13 receives pixel data of a row line which has been readout-controlled by the row selection circuit 12 through a signal output line LSGN, and then the data is transferred to a subsequent stage signal processing circuit.
The readout circuit 13 includes a correlated double sampling (CDS) circuit or analog digital converter (ADC).
FIG. 2 is a diagram illustrating an example of a pixel circuit of CMOS image sensor which is configured of four transistors.
A pixel circuit 20 includes, for example, a photoelectric conversion element 21 (hereinafter, sometimes simply referred to as PD) formed of a photo-diode (PD). With respect to this one photoelectric conversion element 21, the pixel circuit 20 has four transistors as active elements such as a transfer transistor 22, a reset transistor 23, amplification transistor 24, and a selection transistor 25.
The photoelectric conversion element 21 performs a photoelectric conversion of an incident light into an amount of charge (in this case, electrons) corresponding to an amount of light thereof.
The transfer transistor 22 is connected between the photoelectric conversion element 21 and the floating diffusion FD (hereinafter, sometimes simply referred to as FD), and a transfer signal (driving signal) TRG is provided to a gate of the transfer transistor 22 through a transfer control line LTRG.
In this way, electrons which are photoelectrically converted by the photoelectric conversion element 21 are transferred to the floating diffusion FD.
The reset transistor 23 is connected between a power line LVDD and the floating diffusion FD, and a reset signal RST is provided to a gate of the reset transistor 23 through the reset control line LRST.
In this way, a potential of the floating diffusion FD is reset to the potential of the power line LVDD.
In the floating diffusion FD, a gate of amplification transistors 24 is connected. The amplification transistor 24 is connected to a signal line 26 (LSGN in FIG. 1) through the selection transistor 25, and configures a source follower with a constant current outside the pixel unit.
Then, an address signal (selection signal) SEL is provided to a gate of the selection transistor 25 through the selection control line LSEL, and then the selection transistor 25 is turned on.
When the selection transistor 25 is turned on, the amplification transistor 24 amplifies a potential of the floating diffusion FD and then outputs a voltage corresponding to the potential thereof to the signal line 26. A voltage output from each pixel through the signal line 26 is output to the readout circuit.
As the pixel reset operation, a charge accumulated in the photoelectric conversion element 21 is transferred to the floating diffusion FD, and is expelled by turning on the transfer transistor 22.
At this time, the floating diffusion FD turns on the reset transistor 22 and expells the charge to the power source side in advance in order to receive the charge of the photoelectric conversion element 21. Alternatively, while the transfer transistor 22 is turned on, there are cases where the reset transistor 23 is turned on in parallel with the transfer transistor 22 being turned on, accordingly the charge is expelled directly to the power source.
This series of operations is simplified and is called “a pixel reset operation” or “a shutter operation”.
On the other hand, in a readout operation, the floating diffusion FD is reset by first turning on the reset transistor 23, and in such a situation, the output thereof is output to the output signal line 26 through the selection transistor 25 which has been turned on. This is referred to as P-phase output.
Next, the charge accumulated in the photoelectric conversion element 21 is transferred to the floating diffusion FD by turning on the transfer transistor 22, the output thereof is output to the output signal line 26. This is referred to as D-phase output.
Taking the difference between the P-phase and the D-phase outside the pixel circuit, a reset noise of the floating diffusion FD is canceled to become an image signal.
By simplifying this series of operations, they are simply called “a pixel readout operation”.
The control lines such as the transfer control line LTRG, the reset control line LRST, and the selection control line LSEL are selectively driven by the row selection circuit 12.
As a configuration of the pixel circuit, in addition to a four transistor configuration (4Tr-type), configurations such as a three transistor (3Tr-type) and a five transistor (5Tr-type) may be adopted.
The 3Tr-type pixel circuit is not provided with the transfer transistor which controls the movement of charge toward the floating diffusion FD from the photoelectric conversion element (PD) 21 according to the potential of the transfer control line LTRG.
Meanwhile, in the semiconductor apparatus having a structure which a plurality of sensors are disposed in an array-type such as the CMOS image sensor, a demand for sophistication and miniaturization of the signal processing has been increasing.
To achieve this, by making a chip with a stacked structure as in, for example, Japanese Unexamined Patent Application Publication No. 2011-159958, a technique has been proposed to integrate a bigger signal processing circuit in the same chip size as until now.
Such a semiconductor apparatus includes a chip mounted with a sensor array that generates an analog signal (hereinafter, referred to as an analog chip), a chip mounted with a logic circuit for signal processing (hereinafter, referred to as digital chip). Further, the semiconductor apparatus, which is a structure connected with a TC(S)V (Through Contact(Silicon)VIA) formed in the analog chip, has been miniaturized by stacking these chips up and down.